Friday, March 8, 2019

3-dimensional (3D) packaging technology Essay

Introduction3-dimensional (3D) packaging engineering is a method employ to provide volumetric packaging solution in products. This technology uses the height, other known as the third or z-dimension, for achieving advanceder levels of integration and process in the products. 3D technology chiefly helps in the space-efficient integration of the multi-media functions in the products.The present tr close among the consumers is to look forbidden for products, having the utmost functionality in the sm each(prenominal)est and ligh audition accomplishable package. This demand for much functions in the smallest volume, calls for spicyer memory capacity, which in swordplay demands more complex and efficient architectures. In addition, the new product designs in digital handbook, cell phones, digital cameras, PDAs and music players, require that these features are coordinated utilise innovative technical form factors and architectures.See more societal process essayThe 3D packagin g in recent generation has been associated with the delivering of the grittyest level of ti integration and champaign efficiency at the worst cost, smallest size and best performance. This has resulted in higher crop and brought in newer coverings, for the technology.This growth trend in the 3D technology basin be seen since the grade 1995. Prior to this, the most efficient and economic way to provide more functionality to an electronic brass was to integrate all these functions onto the individual micro chips using the system on Chip, SOC. However, this method was becoming costlier and also less efficient, as the sum of functions to be integrated in a single chip encourage increased. In addition, some chips that could be integrated together logically were mechanically incompatible, due to the una comparable return materials employ.The present day technologies in high density packaging befool r individuallyed a truly advanced stage. today a single chip system can be genuinely efficiently split into multiple clog ups, so as to provide s conduce performance at lower manufacturing costs.Over the past few years, die folding has emerged as a superpowerful packaging option for satisfying contend IC packaging requirements. It works by integrating chips straightly in a single package. This increases the amount of silicon per unit ambit, which leads to a littler package footprint, hence conserving system-board real estate. In addition, it enables shorter routing interconnects from chip to chip, speeding the signalize among them. Heterogeneous devices can also be load up using this technology. There is an additional benefit of the simplification of control surface-mount system-board assembly, due to the lesser subject of components being placed on the board.Vias Due to the assortment magnitude number of dies in a mint candy, the designers are facing the challenge of meeting the temperature design limitedation. unitary method to coun ter this is to provide a caloric path from each individual die to a substrate using thermic vias. These thermal vias can be implemented using several methods. One of the approaches is to have a thermal die that thermally connects each die to the substrate.The raise uping from each die is conducted rapidly from one end of the board to another, all through the die attach or the vias. Thermal vias are throw of copper runs providing the a path of least(prenominal) thermal resistance, and so stir up is channelred through the vias in a proportion much greater than the area of the vias. Usually one end of via is attached to the IC and the other end is attached to a awaken sink. Thermal vias work very easily with flip-chip devices. With no additional space required for the heat conduction, these are considered as a mini-thermal solution.Through Silicon Vias Through silicon vias, TSVs, are vertical structures in among the chips that are used as an interconnection to extirpate th e existing wire bonds. These allow for the shortest electrical path between deuce sides of wafers or die, used for 3D die-to-die, die-to-wafer, MEMS wafer level packaging. A TSV, 3-D chip stacking process hence provides a means of implementing complex, multi chip systems entirely in silicon. TSVs. By the vertical stacking of the blocks using this technology, the wire length of interconnects can importantly be reduced.Vias provide both electrical and thermal path. In this paper, the thermal sweetener realized by the vias is discussed along with trying to find out a way to remove heat from the dies. The power use to the dies is between 5-10 watts power. We found that one such method was to use silicon dies. object glass of the StudyThe methodology of the present withdraw forget be explained in detail in the next section. The study focuses on the followers pointsA study was make on the heat transfer enhancement of the stacked die geometry using Through Silicon vias, TSVs, on the di e flesh out location. Different schemes were studied.The use of the TSVs to reduce the utmost unification temperature accumulated at the wafers was studiedThe exact placement of vias to optimize thermal management, was doneFinally, a study of the thermo-mechanical issues, which occurred when TSVs are used, was made.MethodologyThe figure below explains the methodology used for this study. First, the package components including the vias were created using Pro /Engineer Wildfire. After this the material dimension was delimitate and the various components were assembled. The entire geometry and the properties were then imported to Ansys workbench. Here, the Boundary conditions were defined and implemented. Finally, the end result, which is the thermal enhancement of the die geometry, was evaluated.Modeling Methodology any(prenominal) devices thermal properties can be expressed as a part of an electrical circuit diagram. If, JA is the thermal resistance between junction, and ambien ce given in /W, then mathematically JA can be expressed as bewlow The geometry is created using Pro-e, as mentioned in the previous section. Here, each element should be saved in the UDF library. This is done, so as to make it possible to retrace various parts for assembly. In this assembly area, the area contact is done using the mate option, and the vertical and horizontal lines can be joined using the align option.For the analysis, a molded fruitcake Grid Array, BGA, stacked package has been considered. The package substrate is 99 mm in area and is 0.3 mm thick. A fully live solder ball matrix with a ball count of 56 and a pitch of 0.8 mm is used. The stand off height aft(prenominal) re menstruum is 0.2 mm. The ponderousness of the mold compound cap is 1.20 mm with the said(prenominal) dimensions as the package substrate. The diameter of the thermal vias is 0.20mm and its oppressiveness is 0.86mm. The stacked packages have 16 vias and 9 vias. This paper compares the juncti on temperature of stacked dice with and without vias.Three different package architectures were modeled, viz. a Stacked with spacers die, b Rotated stack die, b Pyramid stack die as shown in figure. Three non-volatile dies measuring 6.44.8 mm, with a ponderousness of 0.2 mm, form the spacer die. Die thickness is 0.25mm in rotated die. The keister PCB is made of a die measuring 3224 mm, with a thickness of 0.6 mm. In the spacer stack die, dummy die is 5.64.0, with a thickness of 0.08mm.For this paper, solderball geometry is modeled closely approximating the real solderball. In solderball geometry, mid diameter is 0.43mm, and wind and fundament diameter is 0.33mm, with a height of 0.33mm. Solderball distance is 0.8mm. These dimensions are not specific to a crabby package. They are based on values found in present market for a typical molded BGA stack package. The details of the package dimensions and material properties of the components is shown in the below.Simulation and bap tistery Studies eyepatch doing the Simulation using the Ansys workbench, the following boundary conditions need to be utilize to all the faces of the modeling and to the PCB. The film coefficient is 10W/m C and the Ambient Temperature is 50C. Also a power of 0.3 W ia employ to each of the deuce-ace dies. By dividing area 0.3W / 6.54.8 (Die area), we can get a heat flow as 9765 W/m.The main physics behind the technology is providing a smooth and effective heat transfer path. Due to the high thermal conductivity of the copper i.e. the thermal vias, a proportion of the heat much greater than the surface area of the vias will be transferred.As mentioned in the section to a higher place, for the baseline simulation, an effective heat transfer coefficient of 10 W/m-C with 50c ambient temperature was utilize on the top of the mold cap, and the top and commode surfaces of the circuit board. For all the three types of stacks, the result was a junction temperature of 116.2C with no via s. When 9 vias were included, for the similar heat transfer coefficient, the junction temperature was reduced to 111.7C, results in a decrease of around 3.6% of the level best temperature in each of the architectures. By increasing via count to 16 we got the junction temperature to 110.7C effectively reducing the junction temperature by 4.49% of the upper limit temperature in each of packaging.The figure below explains the proportionate vector plot of heat coalesce in ANSYS Workbench, where the heat flow path can be seen, which densely collects at the via location. This heat flux is a negative heat flux which is flowing away from the surface and takes away energy out of the body in the form of heatVias can also provide a means of customizing the heat transfer process for devices with a highly non-uniform power distribution. This is especially important for high density interconnects where the device has highly non-uniform power map.Test CasesThere were 12 baptismal font studies conducted on the simulation test tool. As mentioned earlier, each matter was tested with and without vias, and the corresponding temperature plot was drawn. In each case the maximal and stripped-down temperatures achieved were also noted. For one of the cases it was found that the particular test case no 11 gave a lesser temperature, in the range of 60-70 degrees.The following is a description of the 12 test casesCase 1 The for the first time case consisted of the Dies showing the temperature plot at the film coefficient of 200W/mC. The power applied to the top die, die with vias and the bottom die was 6watts, 2watts, and 2 watts respectively. The level best temperature achieved was 316.459 C and the minimum temperature was 269.908 C. Applying same conditions without vias gave the level best temperature as 317.2 C and minimum temperature as 269.591 C.Case 2 For the second case, the Boundary conditions applied were a film co-efficient of 200W/mc and Power of 2 watts applied as on all the three dice. The maximum temperature achieved was 216.363 C and the minimum temperature was 169.568 C. Applying same conditions without vias gave the maximum temperature as 217.140 C and minimum temperature as 169.55 C.Case 3 For this case, copper was used as the substrate mask and the film coefficient was cd W/mc. The maximum temperature achieved was 178.739 C and the minimum temperature was 144.488 C. Applying same conditions without vias gave the maximum temperature as 179.426 C and minimum temperature as 144.463 C. The Observation of the above results showed that the temperature dispute with and without Vias was just now 1C.Case 4 For this case, convection was applied on board and top die. The power applied to on top, middle and bottom dies was 4watts, 3watts, and 3watts respectively. The maximum temperature achieved was 93.775 C and the minimum temperature was 36.098 C. Applying same conditions without vias gave very slight convince in the plot, the maximum temperature as 93.911 C and minimum temperature as 36.105 C.Case 5 For this case, the charter co-efficient of 400W/mc on top of the top die and 15W/mc on the Pwb. Also 5watts power was applied to each of the dies. The maximum temperature achieved was 209.345 C and the minimum temperature was 128.857 C. It was seen that the minimum Temperature occurs at the top die where the vias were present. Applying same conditions without vias gave very slight compound in the plot, the maximum temperature as 210.878 C and minimum temperature as 128.739 C, i.e. a drop of only 1.6 C was observed.Case 6 For this case, germanium die was used, instead of silicon die. The maximum temperature achieved was 223.052 C and the minimum temperature was 118.468 C. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 225.219 C and minimum temperature as 118.286 C, i.e. a drop of 2.6 C in the Junction temperature was observed.Case 7 For this case, the drive co-efficient on board was 300 W/mc, the Film co-efficient on top surface was 400W/mc, and 5 watts power applied on both dies. The maximum temperature achieved was 119.575 C and the minimum temperature was 43.411 C. Applying same conditions without vias gave the maximum temperature as 120.076 C and minimum temperature as 43/504 C. The maximum change in Junction temperature, with and without vias was observed.0.5 C.Case 8 In this case, a very high thermal semiconductive material has been used For the through silicon vias (ie.600 W/mc). The maximum temperature achieved was 119.575 C and the minimum temperature was 43.411 C. Applying same conditions without vias gave the maximum temperature as 95.315 C and minimum temperature as 36.347 C. The maximum temperature between i.e. a drop of 2.6 C in the Junction temperature was observed.0.5 C. Though high conductive vias were used there is no significant drop in the maximum temperature in the dice.Case 9 The following case used TSVs with t he application of higher power( 7 watts) on the top die than the Other devil dice i.e.., 2 watts on the die with vias and 1 watt on the bottom Die. The maximum temperature achieved was 97.657 C and the minimum temperature was 39.063 C. Applying same conditions without vias gave the maximum temperature as 97.889 C and minimum temperature as 39.032 C. As seen, the TSVs made a vnegligile difference of 0.5 C.Case 10 In this case, the total power on the dice was 5 watts and the power on the die with vias was 5 watts. The maximum temperature achieved was 61.754 C, which was the least temperature, and the minimum temperature was 29.576 C. Applying same conditions without vias gave the maximum temperature as 61.871 C and minimum temperature as 29.55 C.Case 11 In this case, the substrate and substrate mask thickness is drastically reduced to 0.075mm and 0.085mm. The maximum temperature achieved was 93.697 C and the minimum temperature was 36.079 C. Applying same conditions without vias gav e the maximum temperature as 93.775 C and minimum temperature as 36.067 C.Case 12 In this case, the simulation was done by applying high power of 6 watts on the top die and 2 watts each on the middle and bottom die. The maximum temperature achieved was 88.320 C and the minimum temperature was 35.481 C. Applying same conditions without vias gave the maximum temperature as 88.512 C and minimum temperature as 35.445 C.ConclusionIn this paper elaborate study has been done in analyzing the effect of thermal vias on the die and shipway to bring down the junction temperature by reduce count. Thermal enhancement was tested by running the thermal simulation with various test cases, and also with / without thermal vias. The Temperature profile of the entire stacked die geometry was plan in Ansys Workbench.It was found that Thermally Through Silicon vias in this particular package did not give a significant effect on performance because of less area of vias and package construction. The use of silicon die did give a lesser temperature as compared to other materials.Future studies will focus on doing the stress analysis of this package with vias, using techniques like thermal shocks for profiling the thermal properties this package in further detail.

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